DocumentCode
2544989
Title
Deeper Bound in BMC by Combining Constant Propagation and Abstraction
Author
Armoni, Roy ; Fix, Limor ; Fraer, Ranan ; Heyman, Tamir ; Vardi, Moshe ; Vizel, Yakir ; Zbar, Yael
fYear
2007
fDate
23-26 Jan. 2007
Firstpage
304
Lastpage
309
Abstract
The most successful technologies for automatic verification of large industrial circuits are bounded model checking, abstraction, and iterative refinement. Previous work has demonstrated the ability to verify circuits with thousands of state elements achieving bounds of at most a couple of hundreds. In this paper we present several novel techniques for abstraction-based bounded model checking. Specifically, we introduce a constant-propagation technique to simplify the formulas submitted to the CNF SAT solver; we present a new proof-based iterative abstraction technique for bounded model checking; and we show how the two techniques can be combined. The experimental results demonstrate our ability to handle circuit with several thousands state elements reaching bounds nearing 1,000.
Keywords
computability; formal verification; integrated circuit modelling; iterative methods; logic design; CNF SAT solver; abstraction-based bounded model checking; automatic verification; constant propagation; iterative refinement; large industrial circuits; proof-based iterative abstraction; state elements; Algorithm design and analysis; Automatic logic units; Boolean functions; Costs; Coupling circuits; Data structures; Error correction; Iterative algorithms; Logic circuits; Refining;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific
Conference_Location
Yokohama
Print_ISBN
1-4244-0629-3
Electronic_ISBN
1-4244-0630-7
Type
conf
DOI
10.1109/ASPDAC.2007.358003
Filename
4196049
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