• DocumentCode
    254519
  • Title

    Acceleration of Naive-Bayes algorithm on multicore processor for massive text classification

  • Author

    Lijun Zhou ; Zhiyi Yu ; Jie Lin ; Shikai Zhu ; Weijing Shi ; Haijie Zhou ; Kunpeng Song ; Xiaoyang Zeng

  • Author_Institution
    State-Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
  • fYear
    2014
  • fDate
    10-12 Dec. 2014
  • Firstpage
    344
  • Lastpage
    347
  • Abstract
    Naive-Bayes algorithm acts as a key baseline of massive text classification, which is widely used in fields of detecting spam, online marketing and so on. Multicore processor is a suitable platform to implement Naive-Bayes because of its flexibility, high performance, and energy-efficiency. This paper proposes a new hopscotch hash scheme to improve the performance of data storing and indexing of Naive-Bayes algorithm, and presents a software implementation of Naive-Bayes text classification mapped in Topo-MapReduce model on a multicore processor with circuit switching and packet switching. Experimental results show that the improved hopscotch hash speeds up by 33% at maximum compared to the original hash, and the proposed Topo-MapReduce speeds up the Naive-Bayes algorithm by 29% at maximum compared to the original MapReduce.
  • Keywords
    Bayes methods; multiprocessing systems; pattern classification; text analysis; Topo-MapReduce model; hopscotch hash scheme; massive text classification; multicore processor; naive-Bayes algorithm; software implementation; Acceleration; Computational modeling; Data models; Indexing; Multicore processing; MapReduce; Naive-Bayes algorithm; hopscotch hash; massive text classification; mulitcore processor;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Integrated Circuits (ISIC), 2014 14th International Symposium on
  • Conference_Location
    Singapore
  • Type

    conf

  • DOI
    10.1109/ISICIR.2014.7029490
  • Filename
    7029490