A modified high-radix scalable Montgomery multiplier

Author

Fan, Yibo ; Zeng, Xiaoyang ; Yu, Yu ; Wang, Gang ; Zhang, Qianling

Author_Institution

State-Key Lab of ASIC & Syst., Fudan Univ., Shanghai

fYear

2006

fDate

21-24 May 2006

Lastpage

3385

Abstract

This paper proposed a high-radix scalable Montgomery multiplier with the efficient data-path and half latency. By using new algorithm proposed by this paper, it achieves shorter critical path by calculating coefficient q_Y and q_M in parallel. The algorithm can also provide half latency by changing pipeline dataflow through operands dynamic extending during calculation. This design can be used to accept any input precision up to the size of the on-chip memory. An ASIC implementation in 0.25 mun CMOS technology can perform 1024-bit RSA encryption with 390k bps under 180MHz frequency

Keywords

CMOS logic circuits; application specific integrated circuits; cryptography; digital arithmetic; multiplying circuits; 0.25 micron; 1024 bit; 390 kbit/s; CMOS technology; RSA encryption; application specific integrated circuits; high-radix scalable Montgomery multiplier; on-chip memory; pipeline dataflow; Application specific integrated circuits; CMOS technology; Coprocessors; Delay; Frequency; Internet; Irrigation; Pipelines; Public key cryptography; Tellurium;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693351

Filename

1693351