DocumentCode
2545292
Title
BddCut: Towards Scalable Symbolic Cut Enumeration
Author
Ling, Andrew C. ; Zhu, Jianwen ; Brown, Stephen D.
Author_Institution
Dept. Electr. & Comput. Eng., Toronto Univ., Ont.
fYear
2007
fDate
23-26 Jan. 2007
Firstpage
408
Lastpage
413
Abstract
While the covering algorithm has been perfected recently by the iterative approaches, such as DAOmap and IMap, its application has been limited to technology mapping. The main factor preventing the covering problem´s migration to other logic transformations, such as elimination and resynthesis region identification found in SIS and FBDD, is the exponential number of alternative cuts that have to be evaluated. Traditional methods of cut generation do not scale beyond a cut size of 6. In this paper, a symbolic method that can enumerate all cuts is proposed without any pruning, up to a cut size of 10. We show that it can outperform traditional methods by an order of magnitude and, as a result, scales to 100K gate benchmarks. As a practical driver, the covering problem applied to elimination is shown where it can not only produce competitive area, but also provide more than 6times average runtime reduction of the total runtime in FBDD, a BDD based logic synthesis tool with a reported order of magnitude faster runtime than SIS and commercial tools with negligible impact on area.
Keywords
logic CAD; BddCut; FBDD; covering algorithm; logic synthesis; logic transformations; resynthesis region identification; scalable method; symbolic cut enumeration; Application software; Binary decision diagrams; Boolean functions; Circuit synthesis; Data structures; Iterative algorithms; Iterative methods; Logic; Runtime; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific
Conference_Location
Yokohama
Print_ISBN
1-4244-0629-3
Electronic_ISBN
1-4244-0630-7
Type
conf
DOI
10.1109/ASPDAC.2007.358020
Filename
4196066
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