A reconfigurable VLSI learning array

Author

Bridges, Seth ; Figueroa, Miguel ; Hsu, David ; Diorio, Chris

Author_Institution

Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA

fYear

2005

fDate

12-16 Sept. 2005

Firstpage

117

Lastpage

120

Abstract

We present a reconfigurable array for low-power feedforward neural networks in analog VLSI. This architecture implements a flexible computational model with coarse-grained reconfigurability, and features high computational density for a broad range of applications. Our prototype of the array, fabricated in a 0.35μm process, consumes 0.25mm² of area and dissipates 150μW of power on a 5V supply. In this paper, we discuss the circuits and architecture of our system, as well as experimental results.

Keywords

VLSI; feedforward neural nets; field programmable analogue arrays; low-power electronics; neural chips; reconfigurable architectures; 0.35 micron; 150 muW; 5 V; analog VLSI; coarse-grained reconfigurability; feedforward neural networks; flexible computational model; high computational density; low-power neural network; reconfigurable VLSI learning array; Adaptive control; Computational modeling; Computer architecture; Feedforward neural networks; Field programmable analog arrays; Neural networks; Prototypes; Radial basis function networks; Signal processing algorithms; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European

Print_ISBN

0-7803-9205-1

Type

conf

DOI

10.1109/ESSCIR.2005.1541573

Filename

1541573