An efficient architecture for distributed resampling for high-speed particle filtering

Considering the wide range of applicability of particle filters, their VLSI implementation is of great importance. Resampling is the sequential part of the fully parallel particle filter. Therefore, parallel VLSI architectures for resampling is of particular interest. In this paper, we develop a parallel implementation of resampling. The novel feature of the proposed architecture is that the execution time of resampling becomes independent of the distributions of the weights. Despite the alternatives in the literature, our scheme achieves a very small execution time by pipelining the resampling and sampling steps. Moreover, it is scalable for high levels of parallelism, has lower memory usage, fixed routing time, and has close to ideal performance. Furthermore, it eliminates the need for a point-to-point network between processing elements and results in a simple central unit