High-speed and low-leakage FinFET SRAM cell with enhanced read and write voltage margins

Author

Salahuddin, S.M. ; Kursun, V.

Author_Institution

Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China

fYear

2014

fDate

10-12 Dec. 2014

Firstpage

312

Lastpage

315

Abstract

A new single-ended read asymmetrical SRAM cell with underlap engineered symmetrical FinFETs is proposed in this paper for achieving stronger data stability, enhanced write ability, and suppressed leakage power consumption as compared to previously published six-FinFET memory circuits. With the new SRAM cell, the read data stability, read speed, write voltage margin, and write speed are enhanced by up to 2.7×, 57.6%, 25.5%, and 20.1% while the leakage power consumption is reduced by up to 69.8% without degrading the memory integration density as compared to the previously published six-FinFET SRAM cells in a 15nm FinFET technology.

Keywords

MOSFET; SRAM chips; circuit stability; data stability; enhanced read and write voltage margin; high-speed low-leakage FinFET SRAM cell; leakage power consumption suppression; memory integration density; single-ended read asymmetrical SRAM cell; six-FinFET memory circuit; size 15 nm; underlap engineered symmetrical FinFET technology; Circuit stability; FinFETs; Inverters; Logic gates; Power demand; SRAM cells;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits (ISIC), 2014 14th International Symposium on

Conference_Location

Singapore

Type

conf

DOI

10.1109/ISICIR.2014.7029512

Filename

7029512