Title :
A 220mW 14b 40MSPS gain calibrated pipelined ADC
Author :
Bjornsen, J. ; Moldsvor, Øystein ; Saether, T. ; Ytterdal, Trond
Author_Institution :
Dept. of Electron. & Telecommun., NTNU, Trondheim, Norway
Abstract :
In this paper, a pipelined ADC based on digital calibration of gain errors is presented. The ADC achieves 85dBFS SNDR and 84dBFS SFDR with a 50dB DC gain OTA in the first stage. The calibration algorithm is based on test signal injection. At 40MSPS the power dissipation is 220mW from a 2.5V supply. The ADC is designed in a 0.25μm CMOS process and occupies an area of 6.5mm2.
Keywords :
CMOS integrated circuits; analogue-digital conversion; calibration; operational amplifiers; pipeline processing; 0.25 micron; 2.5 V; 220 mW; 50 dB; CMOS process; calibration algorithm; digital calibration; gain errors; operational transconductance amplifiers; pipelined ADC; test signal injection; Bandwidth; Calibration; Field programmable gate arrays; Filters; Pipelines; Power dissipation; Prototypes; Signal resolution; Testing; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European
Print_ISBN :
0-7803-9205-1
DOI :
10.1109/ESSCIR.2005.1541585
