• DocumentCode
    2545861
  • Title

    A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18μm digital CMOS technology

  • Author

    Tajalli, Armin ; Muller, Paul ; Atarodi, Mojtaba ; Leblebici, Yusuf

  • Author_Institution
    Dept. of Electr. Eng., Sharif Univ. of Technol., Tehran, Iran
  • fYear
    2005
  • fDate
    12-16 Sept. 2005
  • Firstpage
    193
  • Lastpage
    196
  • Abstract
    This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channels achieving an aggregate data rate of 20 Gbps. A structural top-down design methodology has been applied to minimize the power dissipation while satisfying the required specifications for short-haul receivers. Implemented in a 0.18μm digital CMOS technology, total power dissipation is 70.2mW or 3.51mW/Gbps/ch and each channel occupies 0.045μm2 silicon area.
  • Keywords
    CMOS digital integrated circuits; integrated circuit design; low-power electronics; oscillators; radio receivers; 0.18 micron; 20 Gbit/s; 70.2 mW; digital CMOS technology; low-power clock and data recovery circuit; multichannel-gated oscillator; power dissipation minimization; short-haul receivers; structural top-down design; Bandwidth; CMOS technology; Circuit simulation; Circuit topology; Clocks; Delay lines; Frequency; Phase locked loops; Power dissipation; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European
  • Print_ISBN
    0-7803-9205-1
  • Type

    conf

  • DOI
    10.1109/ESSCIR.2005.1541592
  • Filename
    1541592
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2545861