DocumentCode :
2545890
Title :
Design for manufacturing in the nanoscale era
Author :
Bittlestone, Clive
Author_Institution :
Texas Instruments, Dallas, TX, USA
fYear :
2005
fDate :
12-16 Sept. 2005
Firstpage :
197
Abstract :
Design for manufacturing, DFM, has been an increasingly important area for several years. Lithography at 90nm, 65nm, and below takes DFM into the critical zone for designers. Designers must now use extreme measures to achieve full technology entitlement of performance, power, area, reliability and yield. This presentations focus on major physical DFM effects and their impact on designers. It uses real life examples from 90 and 65nm to illustrate problems and trends. Several focus issues are linked to design impact and onto rules, modeling and other mitigation techniques. This talks touch on several critical areas such as RET/OPC/litho/etch, simulation, layout rules, and extraction. Both systematic and random effects are mentioned. Also covered are examples of some methods that are used to model or design around these issues to enable designers to meet technology entitlement goals.
Keywords :
design for manufacture; etching; nanolithography; nanotechnology; proximity effect (lithography); semiconductor process modelling; 65 nm; 90 nm; DFM effects; design for manufacturing; design impact; etching process; layout extraction; mitigation techniques; nanolithography; random effects; simulation process; systematic effects; Area measurement; Design for manufacture; Etching; Instruments; Lithography; Manufacturing; Paper technology; Power measurement; Power system modeling; USA Councils;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European
Print_ISBN :
0-7803-9205-1
Type :
conf
DOI :
10.1109/ESSCIR.2005.1541593
Filename :
1541593
Link To Document :
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