DocumentCode
2545893
Title
A High-Throughput Low-Power AES Cipher for Network Applications
Author
Lin, Shin-Yi ; Huang, Chih-Tsun
Author_Institution
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu
fYear
2007
fDate
23-26 Jan. 2007
Firstpage
595
Lastpage
600
Abstract
We propose a full-featured high-throughput low-power AES cipher which is suitable for widespread network applications. Different modes of operation are implemented, i.e., the ECB, CBC, CTR and CCM modes. Our cipher utilizes a cost-efficient two-stage pipeline for the CCM mode by a single datapath. With the design-for-test circuitry, the maximum throughput is 4.27 Gbps using a 0.13mum CMOS technology with a 333MHz clock rate. The hardware cost is 86.2K gates with the power of 40.9mW.
Keywords
CMOS integrated circuits; cryptography; design for testability; integrated circuit design; low-power electronics; 0.13 micron; 333 MHz; 4.27 Gbits/s; 40.9 mW; CCM mode; CMOS technology; design-for-test circuitry; low-power AES cipher; network applications; two-stage pipeline; Application software; CMOS technology; Circuits; Cryptography; Data security; Hardware; Inverters; Pipelines; Table lookup; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific
Conference_Location
Yokohama
Print_ISBN
1-4244-0629-3
Electronic_ISBN
1-4244-0630-7
Type
conf
DOI
10.1109/ASPDAC.2007.358051
Filename
4196097
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