DocumentCode
2546078
Title
Logic and Layout Aware Voltage Island Generation for Low Power Design
Author
Guo, Liangpeng ; Cai, Yici ; Zhou, Qiang ; Hong, Xianlong
Author_Institution
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing
fYear
2007
fDate
23-26 Jan. 2007
Firstpage
666
Lastpage
671
Abstract
Multiple supply voltage (MSV) is one of the most effective schemes to achieve low power, but most works are based on logic level. A few recent works are based on physical level but all of them do not consider level converters which have an important effect in dual-vdd design. In this work we propose a logic and layout aware approach for voltage assignment and voltage island generation in placement process to minimize the number of level converters and to implement voltage islands with minimal overheads. Experimental results show that our approach uses much less level converters than the approach in (Bin Liu, 2006) (reduced by 59.50% on average) when achieving the same power savings. The approach is able to produce feasible placement with a small impact to traditional placement goals.
Keywords
integrated circuit layout; logic CAD; layout aware voltage island generation; level converters; low power design; placement process; voltage assignment; Added delay; Clustering algorithms; Computer science; Dynamic voltage scaling; Electronic design automation and methodology; Integrated circuit interconnections; Logic design; Power generation; Scattering; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific
Conference_Location
Yokohama
Print_ISBN
1-4244-0629-3
Electronic_ISBN
1-4244-0630-7
Type
conf
DOI
10.1109/ASPDAC.2007.358063
Filename
4196109
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