High-rate quasi-cyclic LDPC codes for magnetic recording channel with low error floor

Author

Zhong, Hao ; Zhang, Tong ; Haratsch, Erich F.

Author_Institution

Dept. of ECSE, Rensselaer Polytech. Inst., Troy, NY

fYear

2006

fDate

21-24 May 2006

Abstract

By implementing an FPGA-based simulator, we investigate the performance of high-rate quasi-cyclic (QC) LDPC codes for the magnetic recording channel at very low sector error rates. Results show that error-floor-free performance can be realized by randomly constructed high-rate regular QC-LDPC codes with column weight 4 for sector error rates as low as 10^-9. We also conjecture several rules for designing randomly constructed high-rate regular QC-LDPC codes with low error floor. We also present a decoder architecture that is well suited to achieving high decoding throughput for these high-rate QC-LDPC codes with low error floor

Keywords

cyclic codes; digital magnetic recording; error statistics; field programmable gate arrays; iterative decoding; parity check codes; FPGA; QC-LDPC codes; decoder architecture; decoding; error floor free performance; magnetic recording channel; quasi-cyclic LDPC codes; AWGN; Error analysis; Error correction codes; Field programmable gate arrays; Hard disks; Iterative decoding; Magnetic recording; Parity check codes; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693392

Filename

1693392