• DocumentCode
    2546334
  • Title

    Semi-iterative analog turbo decoding

  • Author

    Arzel, Matthieu ; Seguin, Fabrice ; Lahuec, Cyril ; Jézéquel, Michel

  • Author_Institution
    GET/ENST de Bretagne, Brest
  • fYear
    2006
  • fDate
    21-24 May 2006
  • Abstract
    This paper presents a novel analog turbo decoding architecture allowing analog decoders for long frame lengths to be implemented on a single chip. This is made possible by suitably using slicing techniques which allow hardware reuse and reconfigurability. The architecture is applied to a DVB-RCS-like code. It shows a reduction of occupied chip area by a factor of ten when compared to a conventional slice design with no significant performance degradation. A single 27mm2 0.25mum BiCMOS decoder can then decode any frame length from 40 up to 1824 bits
  • Keywords
    BiCMOS analogue integrated circuits; analogue circuits; decoding; turbo codes; 0.25 micron; BiCMOS decoder; DVB-RCS-like code; analog decoders; analog turbo decoding architecture; hardware reconfigurability; slicing techniques; 3G mobile communication; BiCMOS integrated circuits; Code standards; Computer architecture; Degradation; Digital video broadcasting; Encoding; Hardware; Iterative decoding; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
  • Conference_Location
    Island of Kos
  • Print_ISBN
    0-7803-9389-9
  • Type

    conf

  • DOI
    10.1109/ISCAS.2006.1693396
  • Filename
    1693396
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2546334