Intra- and inter-chip voltage droop analysis using a power delivery grid model

Connection of power supply for chips and cores is a complex model. Due to both the physical structure of the silicon and the temporal workload, significant voltage variation can be observed at the power grid. Especially, voltage droop can be severe and causes problems, such as signal propagation delay or even faults. Thorough understanding about the cause of voltage droop may give a more reliable prediction on how the power supply varied so the power can be utilized effectively. In this paper, an intra- and inter-chip power delivery model is developed and is used for analyzing the voltage droop with different cores and tasks scheduled. This multi-chip power grid model is an extension from the single chip model and is capable for integrating intra- and interchip networks. To verify the design, we can simulate the synthetic current workloads using SPICE. Based on this model, we can outline that the voltage droop, which can be reduced significantly when the tasks are scheduled with spatial and temporal changes.