Title :
Systematic Scan Reconfiguration
Author :
Al-Yamani, Ahmad A. ; Devta-Prasanna, Narendra ; Gunda, Arun
Author_Institution :
Comput. Eng., KFUPM, Dhahran
Abstract :
We present a new test data compression technique that achieves 10times to 40times compression ratios without requiring any information from the ATPG tool about the unspecified bits. The technique is applied to both single-stuck as well as transition fault test sets. The technique allows aggressive parallelization of scan chains leading to similar reduction in test time. It also reduces tester pins requirements by similar ratios. The technique is implemented using a hardware overhead of a few gates per scan chain.
Keywords :
boundary scan testing; data compression; fault diagnosis; integrated circuit testing; logic testing; scan chains; single-stuck fault test sets; systematic scan reconfiguration; test data compression technique; transition fault test sets; Automatic test pattern generation; Circuit testing; Clocks; Costs; Design for testability; Energy consumption; Flip-flops; Hardware; Instruction sets; Pins;
Conference_Titel :
Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
1-4244-0629-3
Electronic_ISBN :
1-4244-0630-7
DOI :
10.1109/ASPDAC.2007.358075
