Title :
Radiation-hard/high-speed parallel optical links
Author :
Gan, K.K. ; Buchholz, Peter ; Kagan, H. ; Kass, R.D. ; Moore, James ; Smith, D.S. ; Wiese, Andreas ; Ziolkowski, Marek
Author_Institution :
Dept. of Phys., Ohio State Univ., Columbus, OH, USA
fDate :
Oct. 27 2012-Nov. 3 2012
Abstract :
We have designed an ASIC for use in a parallel optical engine for a new layer of the ATLAS pixel detector in the initial phase of the LHC luminosity upgrade. The ASIC is a 12channel VCSEL (Vertical Cavity Surface Emitting Laser) array driver capable of operating up to 5 Gb/s per channel. The ASIC is designed using a 130 nm CMOS process to enhance the radiation-hardness. A scheme for redundancy has also been implemented to allow bypassing of a broken VCSEL. The ASIC also contains a power-on reset circuit that sets the ASIC to a default configuration with no signal steering. In addition, the bias and modulation currents of the individual channels are programmable. We have received the ASIC and the performance up to 5 Gb/s is satisfactory. Furthermore, we are able to program the bias and modulation currents and to bypass a broken VCSEL channel. We are currently upgrading our design to allow operation at 10 Gb/s per channel yielding an aggregated bandwidth of 120 Gb/s. Some preliminary results of the design will be presented.
Keywords :
CMOS integrated circuits; application specific integrated circuits; optical links; radiation hardening (electronics); redundancy; semiconductor laser arrays; surface emitting lasers; ASIC; ATLAS pixel detector; CMOS process; LHC luminosity upgrade; VCSEL array driver; high-speed parallel optical links; modulation currents; parallel optical engine; power-on reset circuit; radiation-hard parallel optical links; redundancy; size 130 nm; vertical cavity surface emitting laser array driver;
Conference_Titel :
Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2012 IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4673-2028-3
DOI :
10.1109/NSSMIC.2012.6551190