Title :
A study of time redundant fault tolerance techniques for superscalar processors
Author_Institution :
Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA
Abstract :
As more and more transistors are incorporated into processor chips, the circuits are becoming more and more error-prone, necessitating the introduction of fault tolerance techniques. This paper investigates techniques to incorporate fault tolerance in superscalar processors by exploiting the functional unit redundancy available in these processors. The schemes investigated in this paper do not require any modifications to the instruction set architecture of the machine, and no additional instructions are added by the compiler. The paper also presents the results of a simulation study that we conducted to analyze the performance impact of the investigated fault tolerance schemes
Keywords :
VLSI; fault tolerant computing; instruction sets; microprocessor chips; processor scheduling; redundancy; dynamic scheduling; functional unit redundancy; instruction set architecture; performance impact; superscalar processors; time redundant fault tolerance techniques; Circuits; Computer errors; Decoding; Dynamic scheduling; Fault tolerance; Fault tolerant systems; Hardware; Parallel processing; Redundancy; Very large scale integration;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1995. Proceedings., 1995 IEEE International Workshop on,
Conference_Location :
Lafayette, LA
Print_ISBN :
0-8186-7107-6
DOI :
10.1109/DFTVS.1995.476954
