• DocumentCode
    2546544
  • Title

    Expandable hardware for computing cortical feature maps

  • Author

    Shi, Bertram E. ; Tsang, Eric K C ; Lam, Stanley Y M ; Meng, Yicong

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol.
  • fYear
    2006
  • fDate
    21-24 May 2006
  • Abstract
    We describe expandable hardware architecture for the rapid simulation of feature maps inspired by the visual cortex. Feature maps are retinotopically organized arrays of neurons selective to different combinations of visual features. The responses of these maps are believed to be important for the brain to merge information from different visual cues. This architecture is based around a custom designed board containing DSP and FPGA chips. It is modular in the sense that additional boards can be integrated into the system to accommodate cortical models of increasing complexity
  • Keywords
    biocomputing; brain; field programmable gate arrays; neural nets; DSP chips; FPGA chips; brain; cortical feature maps; cortical models; expandable hardware architecture; neuron arrays; retinotopically organized arrays; visual cortex; Brain modeling; Computer architecture; Digital signal processing chips; Filtering; Frequency; Hardware; Neurons; Nonlinear filters; Retina; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
  • Conference_Location
    Island of Kos
  • Print_ISBN
    0-7803-9389-9
  • Type

    conf

  • DOI
    10.1109/ISCAS.2006.1693407
  • Filename
    1693407