• DocumentCode
    2546700
  • Title

    Towards a Systematic, Pragmatic and Architecture-Aware Program Optimization Process for Complex Processors

  • Author

    Parello, David ; Temam, Olivier ; Cohen, Albert ; Verdun, Jean-Marie

  • Author_Institution
    HP France and HiPEAC network
  • fYear
    2004
  • fDate
    06-12 Nov. 2004
  • Firstpage
    15
  • Lastpage
    15
  • Abstract
    Because processor architectures are increasingly complex, it is increasingly difficult to embed accurate machine models within compilers. As a result, compiler efficiency tends to decrease. Currently, the trend is on top-down approaches: static compilers are progressively augmented with information from the architecture as in profile-based, iterative or dynamic compilation techniques. However, for the moment, fairly elementary architectural information is used. In this article, we adopt a bottom-up approach to the architecture complexity issue: we assume we know everything about the behavior of the program on the architecture. We present a manual but systematic process for optimizing a program on a complex processor architecture using extensive dynamic analysis, and we find that a small set of run-time information is sufficient to drive an efficient process. We have experimentally observed on an Alpha 21264 that this approach can yield significant performance improvement on Spec benchmarks, beyond peak Spec. We are currently using this approach for optimizing customer applications.
  • Keywords
    Design optimization; Dynamic compiler; Genetic algorithms; Information analysis; Iterative methods; Operations research; Performance analysis; Program processors; Runtime; Tiles;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Supercomputing, 2004. Proceedings of the ACM/IEEE SC2004 Conference
  • Print_ISBN
    0-7695-2153-3
  • Type

    conf

  • DOI
    10.1109/SC.2004.61
  • Filename
    1392945