Title :
Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology
Author :
Chung, B. ; Kuo, J.B.
Author_Institution :
Sch. of Eng. Sci., SFU, Burnaby, BC
Abstract :
This paper reports a novel gate-level dual-threshold static power optimization methodology (GDSPOM), which is based on the static timing analysis technique, for designing high-speed low-power SOC applications using 90nm MTCMOS technology. Based on this optimization technique, using two cell libraries with different threshold voltages, a 16-bit multiplier using the dual-threshold cells meeting the speed requirement has been designed to have a 50% less power consumption as compared to the all low-threshold one
Keywords :
CMOS integrated circuits; high-speed integrated circuits; integrated circuit design; logic design; low-power electronics; multiplying circuits; system-on-chip; 16 bit; 90 nm; MTCMOS technology; cell libraries; dual-threshold cells; gate-level dual-threshold static power optimization methodology; high-speed low-power SOC; multiplier circuits; static timing analysis; system-on-chip; threshold voltages; Circuit testing; Costs; Design methodology; Design optimization; Energy consumption; Libraries; Performance analysis; Propagation delay; Threshold voltage; Timing;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693418
