Title :
Low power low leakage clock gated static pulsed flip-flop
Author :
Seyedi, A.S. ; Rasouli, S.H. ; Amirabadi, A. ; Afzali-Kusha, A.
Author_Institution :
Sch. of Electr. & Comput. Eng., Tehran Univ.
Abstract :
In this paper, a low power low leakage flip-flop called clock gated static pulsed flip-flop (CGSPFF) is proposed. The dynamic power consumption in CGSPFF is reduced by avoiding unnecessary input pulse transitions with clock gating. Two transistors in the main block of the flip-flop are eliminated to achieve low leakage power as well. Using the new clock pulse generator leads to a higher operational speed and lower power consumption compared to the previously proposed flip-flops. The results of the simulation show that the PDP of the proposed flip-flop is reduced by at least 58.3%
Keywords :
VLSI; clocks; flip-flops; low-power electronics; power consumption; PDP; clock gated static pulsed flip-flop; clock gating; clock pulse generator; input pulse transition; low power low leakage flip-flop; power consumption; CMOS technology; Capacitance; Circuits; Clocks; Delay; Energy consumption; Flip-flops; Latches; Leakage current; Pulse generation;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693420
