Mapping DSP applications on processor/coarse-grain reconfigurable array architectures

Results from mapping five real-world DSP applications on a system-on-chip that incorporates coarse-grain reconfigurable hardware with an instruction-set processor is presented. The reconfigurable logic is realized by a 2-dimensional array of processing elements. A mapping method for improving application´s performance by accelerating critical software parts, called kernels, on the coarse-grain reconfigurable array is proposed. For mapping the detected kernels on the reconfigurable logic a priority-based mapping algorithm has been developed. Important overall application speedups, due to the kernels´ acceleration, have been reported for the five applications. These overall performance improvements range from 1.27 to 3.07, with an average value of 2.16, relative to an all-software execution