Superpipelined reconfigurable hardware for DSP

Reconfigurable hardware offers a number of advantages over custom integrated circuits, including low development cost, high flexibility, and high adaptability to changing requirements. However, this alternative does incur some reduction in performance, especially for computationally intensive tasks such as digital signal processing. Recent developments in both research and industry have aimed to reduce this gap. This paper introduces a novel reconfigurable architecture that pipelines computations at the bit level. The architecture includes a number of features to improve performance, including medium-grain cells, hierarchical interconnections, and minimal clocking overhead. Circuit simulations demonstrate that the basic cell runs at 1.5 GHz in a modest 180-nm technology. At this speed, we estimate that the device could compute a 256-point fast Fourier transform in 829 ns