DocumentCode :
2546842
Title :
Superpipelined reconfigurable hardware for DSP
Author :
Myjak, Mitchell J. ; Delgado-Frias, José G.
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA
fYear :
2006
fDate :
21-24 May 2006
Abstract :
Reconfigurable hardware offers a number of advantages over custom integrated circuits, including low development cost, high flexibility, and high adaptability to changing requirements. However, this alternative does incur some reduction in performance, especially for computationally intensive tasks such as digital signal processing. Recent developments in both research and industry have aimed to reduce this gap. This paper introduces a novel reconfigurable architecture that pipelines computations at the bit level. The architecture includes a number of features to improve performance, including medium-grain cells, hierarchical interconnections, and minimal clocking overhead. Circuit simulations demonstrate that the basic cell runs at 1.5 GHz in a modest 180-nm technology. At this speed, we estimate that the device could compute a 256-point fast Fourier transform in 829 ns
Keywords :
digital signal processing chips; fast Fourier transforms; multiprocessor interconnection networks; pipeline processing; reconfigurable architectures; 1.5 GHz; 180 nm; 829 ns; circuit simulations; digital signal processing; fast Fourier transforms; pipeline architecture; reconfigurable architecture; superpipelined reconfigurable hardware; Application specific integrated circuits; Circuit simulation; Clocks; Computer architecture; Costs; Digital signal processing; Hardware; Integrated circuit interconnections; Pipelines; Reconfigurable architectures;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
Type :
conf
DOI :
10.1109/ISCAS.2006.1693423
Filename :
1693423
Link To Document :
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