A stream register file unit for reconfigurable processors

Author

Campi, F. ; Zoffoli, P. ; Mucci, C. ; Bocchi, M. ; Deledda, A. ; De Dominicis, M. ; Vitkovski, A.

Author_Institution

STMicroelectronics, Agrate Brianza

fYear

2006

fDate

21-24 May 2006

Abstract

This paper presents a local buffer memory in the form of a stream register file (SRF) that was developed in order to connect, in a compiler-friendly pattern, large-bandwidth run-time configurable logic units in processor-based SOCs. The proposed SRF offers to the host SOC system performance speedups in the range of 4times, with area/power overhead in the order of 6%. The described hardware and algorithm mapping strategy was implemented on silicon in a SOC based on the PiCoGA reconfigurable architecture. The SOC provides an average 450 MOPS (mega operations per Second) in STM CMOS090 technology running at 100MHZ

Keywords

buffer storage; microprocessor chips; reconfigurable architectures; system-on-chip; PiCoGA reconfigurable architecture; SOC; algorithm mapping; buffer memory; hardware mapping; reconfigurable processors; run-time configurable logic units; stream register file; Computer architecture; Hardware; Logic design; Logic devices; Parallel processing; Reconfigurable architectures; Reconfigurable logic; Registers; Runtime; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693425

Filename

1693425