QED post-silicon validation and debug: Invited abstract

Summary form only given. This paper presents the Quick Error Detection (QED) technique for systematically creating families of post-silicon validation tests that quickly detect bugs inside processor cores and uncore components (cache controllers, memory controllers, on-chip interconnection networks) of multi-core System on Chips (SoCs). Such quick detection is essential because long error detection latency, the time elapsed between the occurrence of an error due to a bug and its manifestation as an observable failure, severely limits the effectiveness of traditional post-silicon validation approaches. QED can be implemented completely in software, without any hardware modification. Hence, it is readily applicable to existing designs. Results using multiple hardware platforms, including the Intel® Core™ i7 SoC, and a state-of-the-art commercial multi-core SoC, along with simulation results using an OpenSPARC T2-like multi-core SoC with bug scenarios from commercial multi-core SoCs demonstrate: 1. Error detection latencies of post-silicon validation tests can be very long, up to billions of clock cycles, especially for bugs inside uncore components. 2. QED shortens error detection latencies by up to 9 orders of magnitude to only a few hundred cycles for most bug scenarios. 3. QED enables up to a 4-fold increase in bug coverage.