DocumentCode :
254703
Title :
A user´s reflections on the art of high level synthesis
Author :
Yu Pan ; Pilakkat, S.K. ; Benny Tan, K.-C. ; Wai-Meng Mok
Author_Institution :
Eng. Dept., A*STAR Singapore, Singapore, Singapore
fYear :
2014
fDate :
10-12 Dec. 2014
Firstpage :
67
Lastpage :
70
Abstract :
“It worked perfectly on the demo programs, but just doesn´t work for slightly complicated code”. One of our researchers commented this on his previous experience with High Level Synthesis (HLS). On the other hand, when I first preached to one of our hardware engineers to use HLS, he was immediately sold after I told him that HLS can perform automatic pipelining. After decades of academic and industrial research and development, and several waves of commercial attempts, robust HLS tool flows that are able to generate high performance hardware blocks, perform rapid design space exploration and ease design verifications are finally upon us. While universities and major industrial companies begin to adopt and incorporate HLS into their standard design repertoire [1], many more have not been aware of or experienced this paradigm shift. In this talk, we argue that it is time to start HLS, and share our experience and reflections from our recent first hand close contact with state-of-the-art commercial HLS tools in our product development cycle.
Keywords :
high level synthesis; design space exploration; design verifications; high level synthesis; product development cycle; robust HLS tool; user reflections; Algorithm design and analysis; Data processing; Hardware; High level synthesis; Signal processing algorithms; Software; Throughput; HLS; design; engineering; modeling; programming;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Integrated Circuits (ISIC), 2014 14th International Symposium on
Conference_Location :
Singapore
Type :
conf
DOI :
10.1109/ISICIR.2014.7029585
Filename :
7029585
Link To Document :
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