DocumentCode
254705
Title
A real-time silicon cerebellum spiking neural model based on FPGA
Author
Junwen Luo ; Coapes, G. ; Degenaar, P. ; Yamazaki, T. ; Mak, T. ; Chung Tin
Author_Institution
Sch. of Electr. & Electron. Eng., Newcastle Univ., Newcastle upon Tyne, UK
fYear
2014
fDate
10-12 Dec. 2014
Firstpage
276
Lastpage
279
Abstract
Sensorimotor control and learning require the function of sophisticated neural system. Cerebellum is one such brain region which comprises more than half of the total neuron population in the entire brain. Capable of simulating a bio-realistic cerebellum model provides important information for neuroscience and engineering. Here we present a Network-on-Chip (NoC) hardware architecture for implementing a bio-realistic cerebellum model of passage-of-time (POT) encoding with 100,000 neurons. The results demonstrate that our implementation can reproduce the POT functionality properly. The maximum computational speed can reach 25.6 ms for simulating 1 sec real world activities. Our silicon cerebellum can be readily interface with in vivo or in vitro experiment and be adapted as a potential neuroprosthetic platform for future biological or clinical applications.
Keywords
field programmable gate arrays; network-on-chip; neural nets; FPGA; NoC hardware architecture; POT encoding; bio-realistic cerebellum model; network-on-chip; neuroprosthetic platform; passage-of-time encoding; real-time silicon cerebellum spiking neural model; Brain modeling; Computational modeling; Computer architecture; Hardware; Integrated circuit modeling; Microprocessors; Neurons; Cerebellum; FPGA; Network on chip; Passage-of-time;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuits (ISIC), 2014 14th International Symposium on
Conference_Location
Singapore
Type
conf
DOI
10.1109/ISICIR.2014.7029586
Filename
7029586
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