Exploration of Low Power Adders for a SIMD Data Path

Hardware for ambient intelligence needs to achieve extremely high computational efficiency (up to 40GOPS/W). An important way for reaching this is exploiting parallelism, and more specifically data-level parallelism enabled by SIMD. Whereas a large body of research exists on the benefits of the architectural design of and compilation onto SIMD, the design of energy-optimal functional units for SIMD has received limited attention. It appears that existing SIMD functional units are designed in an area optimal, but not energy optimal way. By exploiting the difference in critical path length for the types of operations (e.g., 4times8/2times16/1times32), SIMD adders can be developed that save up to 40% of energy. In this paper, the authors present these adders, the issues of building them and quantify their benefits for different usage scenarios and operating frequencies.