Title :
Investigation of inductors for digital Si-CMOS technologies
Author :
Mukhopadhyay, R. ; Yoon, S.-W. ; Park, Y. ; Lee, C.-H. ; Nuttinck, S. ; Laskar, J.
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA
Abstract :
This paper investigates the performance of passive and active inductors for digital Si-CMOS technologies. The extreme low-resistivity of the Si-substrate and the absence of thick top metal layers in digital-CMOS processes prevent the implementation of high-Q passive inductors, and demand alternate solutions. A detailed comparison between the active and passive inductors based on several performance criteria such as Q-factor, area, tunability, noise, linearity, EMI, floor-planning etc reveals the tremendous potential of the high-Q tunable active inductors. An optimization guideline for the grounded-inductor topology has also been suggested. As a basis of comparison, oscillators have been implemented using both the inductors. The active inductor VCO achieves a much higher tuning range and occupies a much smaller die-area than the passive implementation at the cost of degraded phase-noise performance
Keywords :
CMOS digital integrated circuits; circuit optimisation; inductors; network topology; silicon; voltage-controlled oscillators; VCO; digital Si-CMOS technologies; digital-CMOS processes; grounded-inductor topology; high-Q passive inductors; high-Q tunable active inductors; phase-noise performance; Active inductors; Active noise reduction; Costs; Electromagnetic interference; Guidelines; Linearity; Q factor; Topology; Tuning; Voltage-controlled oscillators; Active inductor; EMI; VCO; digital Si-CMOS; floor-planning; linearity; phase-noise; quality-factor; spiral inductor; tunability; tuning range;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693443