DocumentCode :
2547466
Title :
A 10mW 81dB cascaded multibit quadrature ΣΔ ADC with a dynamic element matching scheme
Author :
Maurino, Roberto ; Papavassiliou, Christos
Author_Institution :
Analog Devices, Berkshire, UK
fYear :
2005
fDate :
12-16 Sept. 2005
Firstpage :
451
Lastpage :
454
Abstract :
A multibit 2-0 cascaded quadrature ΣΔ modulator is presented which attains 81 dB dynamic range in a 200kHz bandwidth at an IF of 10MHz. A simple dynamic element matching (DEM) scheme minimizes the mirror in-band aliases caused by mismatch between the I and Q channel. The integral nonlinearity (INL) errors from the multibit feedback DAC are noise-shaped by a quadrature variant of the data weighted averaging algorithm (DWA). Clocked at 13.1 MHz, the ADC consumes 10mW from a 2.1 V supply.
Keywords :
sigma-delta modulation; ΣΔ analog-digital converter; 10 MHz; 10 mW; 13.1 MHz; 2.1 V; 200 kHz; cascaded quadrature ΣΔ modulator; data weighted averaging algorithm; dynamic element matching scheme; integral nonlinearity errors; mirror in-band aliases; multibit feedback DAC; Bandwidth; Clocks; Dynamic range; Educational institutions; Feedback; Frequency conversion; Manufacturing; Mirrors; Quantization; Signal to noise ratio;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European
Print_ISBN :
0-7803-9205-1
Type :
conf
DOI :
10.1109/ESSCIR.2005.1541657
Filename :
1541657
Link To Document :
بازگشت