DocumentCode :
2547539
Title :
Design of defect-tolerant scan chains for MCMs with an active substrate
Author :
Brahic, P. ; Leveugle, R. ; Saucier, G.
Author_Institution :
Inst. Nat. Polytech. de Grenoble, France
fYear :
1995
fDate :
13-15 Nov 1995
Firstpage :
252
Lastpage :
260
Abstract :
The work presented in this paper aims at defining the best solution for designing defect-tolerant scan chains, taking into account the sensitivity of the yield improvement on various parameters. The results presented demonstrate that a noticeable yield increase can be achieved, but only if the selected redundant architecture is coherent with the implementation details, in particular the multiplexer electrical structure. It is also shown that the most straightforward approach, i.e., the triple modular redundancy, can be very inefficient if optimized majority gates are not available for the implementation
Keywords :
boundary scan testing; circuit optimisation; integrated circuit packaging; integrated circuit yield; multichip modules; multiplexing; production testing; redundancy; MCMs; active substrate; defect-tolerant scan chains; multiplexer electrical structure; redundant architecture; triple modular redundancy; yield improvement; Electronic mail; Energy consumption; Integrated circuit technology; Manufacturing; Multiplexing; Multiprocessor interconnection networks; Packaging; Redundancy; Silicon; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1995. Proceedings., 1995 IEEE International Workshop on,
Conference_Location :
Lafayette, LA
ISSN :
1550-5774
Print_ISBN :
0-8186-7107-6
Type :
conf
DOI :
10.1109/DFTVS.1995.476959
Filename :
476959
Link To Document :
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