A high performance CAVLC encoder design for MPEG-4 AVC/H.264 video coding applications

Author

Chien, Chih-Da ; Lu, Keng-Po ; Shih, Yi-Hung ; Guo, Jiun-In

Author_Institution

Dept. of Comput. Sci. & Inf. Eng., National Chung Cheng Univ., Chia-Yi

fYear

2006

fDate

21-24 May 2006

Lastpage

3841

Abstract

This paper presents a high performance VLSI architecture design for MPEG-4 AVC/H.264 CAVLC encoding. In the proposed design, we propose a forward-based parallel coding (FPC) technique to increase the data throughput rate. Moreover, two approaches called arithmetic table elimination (ATE) and fast look-up table matching (FLM) are exploited to reduce the hardware cost. With the synthesis constraint of 125 MHz clock, the hardware cost of the proposed design is 9724 gates based on a 0.18mum CMOS technology, which achieves the real-time processing requiremenwat for H.264 video encoding on HD1080 format video

Keywords

CMOS integrated circuits; integrated circuit design; logic design; table lookup; video coding; 125 MHz; CAVLC encoder; CMOS technology; H.264 video coding; HD1080 format video; MPEG-4 AVC video coding; VLSI architecture design; arithmetic table elimination; fast look-up table matching; forward-based parallel coding; Automatic voltage control; CMOS technology; Costs; Encoding; Flexible printed circuits; Hardware; MPEG 4 Standard; Throughput; Very large scale integration; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693465

Filename

1693465