A bit-serial implementation of mode decision algorithm for AVC encoders

Author

Garstecki, Pawel ; Luczak, Adam ; Stepniewska, M.

Author_Institution

Div. of Multimedia Telecommun. & Radioelectronics, Poznan Univ. of Technol.

fYear

2006

fDate

21-24 May 2006

Lastpage

3845

Abstract

The paper presents a new and efficient architecture for H.264/AVC video encoder control. The architecture of mode decision and cost estimation module is implemented with the use of bit-serial arithmetic and provides pipelined processing of image blocks. The module is designed to support FPGA devices. It has been shown that the design is capable to perform at a very low clock speed, thus it is a suitable solution for wireless communications. The proposed modules have been implemented in Verilog HDL and synthesized for a Xilinx Virtex II family device

Keywords

digital arithmetic; encoding; field programmable gate arrays; hardware description languages; microprocessor chips; pipeline processing; video coding; AVC video encoder control; FPGA device; H.264; Verilog HDL; Xilinx Virtex II; bit-serial arithmetic; mode decision algorithm; pipelined image block processing; very low clock speed; wireless communication; Arithmetic; Automatic voltage control; Cost function; Decoding; Encoding; Field programmable gate arrays; Hardware design languages; Streaming media; Video compression; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693466

Filename

1693466