Nanometer MCML gates: models and design considerations

Author

Alioto, Massimo ; Palumbo, Gaetano

Author_Institution

Dipt. di Ingegneria dell´´Informazione, Universita di Siena

fYear

2006

fDate

21-24 May 2006

Abstract

In this paper, analytical models of the static and dynamic behavior of MOS current-mode logic (MCML) with a resistive load are discussed. These models account for deep-submicron (DSM) effects which affect the operation of this CMOS logic style in the nanometer regime. In particular, a noise margin model is derived by resorting to the alpha-power law, and comparison with the long-channel expression allows for clearly understanding the impact of DSM effects. The dynamic behavior is also analyzed by accurately modeling the resistive load, i.e. accounting for its capacitive parasitics, which are shown to give an important contribution in low-power designs. Analytical results and considerations are validated by means of Spectre simulations on a 90-nm CMOS technology

Keywords

CMOS logic circuits; current-mode logic; integrated circuit modelling; integrated circuit noise; logic design; logic gates; low-power electronics; nanoelectronics; 90 nm; CMOS logic style; CMOS technology; MOS current-mode logic; alpha-power law; deep-submicron effects; dynamic behavior; nanometer MCML gates; noise margin model; resistive load; static behavior; Analytical models; CMOS logic circuits; CMOS technology; Circuit noise; Noise generators; Noise reduction; Parasitic capacitance; Pulse inverters; Semiconductor device modeling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693471

Filename

1693471