A 9-b 400 Msample/s pipelined analog-to digital converter in 90nm CMOS

Author

Peach, C.T. ; Ravi, A. ; Bishop, R. ; Soumyanath, K. ; Allstot, D.J.

Author_Institution

Intel R&D, Intel Corp., Hillsboro, OR, USA

fYear

2005

fDate

12-16 Sept. 2005

Firstpage

535

Lastpage

538

Abstract

A 9-bit 400MS/s pipelined analog-to-digital converter (ADC) targeted for emerging wireless LAN applications is presented. The converter can be clocked up to 500 mega-samples per second (MSPS) with an input bandwidth of 100 MHz, while drawing 93mA from 1.5V. The ADC achieves 8.6 effective number of bits (ENOBs) at 10MHz input and 7.9 ENOBs at 80MHz input, without accounting for calibration or oversampling based enhancements. The architecture is a double-sampled switched-capacitor pipeline that converts on both phases of the sampling clock for improved power efficiency. A skew-insensitive sample-and-hold stage attenuates distortion caused by imperfectly phased sampling clocks.

Keywords

CMOS integrated circuits; analogue-digital conversion; pipeline processing; switched capacitor networks; wireless LAN; 1.5 V; 10 MHz; 100 MHz; 80 MHz; 90 nm; 93 mA; CMOS; phased sampling clocks; pipelined analog-to digital converter; sample and hold stage; switched capacitor pipeline; wireless LAN; Analog-digital conversion; Bandwidth; Calibration; Capacitors; Clocks; Pipelines; Sampling methods; Switches; Switching circuits; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European

Print_ISBN

0-7803-9205-1

Type

conf

DOI

10.1109/ESSCIR.2005.1541678

Filename

1541678