Improving Network´s Performability Using Parallel Processing

By occurring failures in computer networks, routing protocols are triggered to update routing and forwarding tables. Because of invalid tables during update-time, transient loop may occur and packet-drop rate and end-to-end delay increase which means that the quality of service decreases. This paper proposes a parallel architecture for a router to recalculate and update routing table. Simulation results show that with dual-processor architecture, this update time could be up to 40% improved, depending on the network topology and the size of tables. This paper also studies the effect of this speed-up on networks´ performability, i.e. the ability to deliver services at predefined level. A sample network is studied and the simulation results show that faster updates of routing table, improves network´s performability in the presence of failures. Since it may not worth or even be practical to improve all routers in the network, this paper suggests finding bottleneck routers and accelerating them in order to improve the performability of the networks. The simulation results show that by speeding-up the bottleneck routers of the network, instead of all routers, the performability still could be improved.