DocumentCode
2548144
Title
Low-power 6-bit flash ADC for high-speed data converters architectures
Author
Ferragina, Vincenzo ; Ghittori, Nicola ; Maloberti, Franco
Author_Institution
Dept. of Electron., Pavia Univ.
fYear
2006
fDate
21-24 May 2006
Abstract
The design of low-power, medium resolution flash converter is presented. The goal is to provide a basic cell with state-of-the art figure of merit thus permitting low-power data converter architectures with a more flexible use of flash ADC cells. The designed 6-bit flash uses interpolation and V/I converters that operate as preamplifier stage of latches. Circuit simulations show a figure of merit as low as 1.2 pj/conv-lev at 100-MS/s sampling frequency and 3.3-V analog supply voltage
Keywords
analogue-digital conversion; flash memories; flip-flops; interpolation; low-power electronics; preamplifiers; 3.3 V; 6 bit; V/I converters; circuit simulations; flash ADC cells; high-speed data converters architectures; low-power data converter architectures; medium resolution flash converter; preamplifier stage; Analog-digital conversion; Circuits; Energy consumption; Frequency; Interpolation; Latches; Preamplifiers; Quantization; Sampling methods; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location
Island of Kos
Print_ISBN
0-7803-9389-9
Type
conf
DOI
10.1109/ISCAS.2006.1693488
Filename
1693488
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