Low power LC-VCO design using direct cross-coupled cell biasing

This paper presents a low power LC-VCO design using a direct cross-coupled cell biasing topology. In the proposed topology, the bias current mirror is directly connected to the gate of the cross-coupled cell that generates a negative resistance, and hence removes the voltage drop in the top- or tail-transistor used for current biasing. A capacitive degenerated buffer stage generates an extra negative resistance and relieves the current requirement for the VCO core, and further reduces the power consumption. The proposed topology is also insensitive to the power supply noise. An example 10 GHz VCO in 0.13 mum CMOS technology drains only 0.6 mA from 1.2 V power supply. It shows 13.6% tuning range and -108 dBc/Hz phase noise at 1 MHz offset. For an operation under 0.8 V power supply with 0.45 mA current, the tuning range and phase noise degrade to 12.3% and -103dBc/Hz at 1 MHz offset respectively