Title :
Architecture of a hypertransport tunnel
Author :
Castonguay, Ami ; Savaria, Yvon
Author_Institution :
Ecole Polytechnique de Montreal, Que.
Abstract :
This paper presents a technology independent and open source hypertransport (HT) tunnel. HT is a high performance and low latency chip-to-chip interconnect standard. Various aspects of the architecture are presented, ranging from how functionality is spread over clock domains to the means of implementing a packet reordering algorithm. The analysis of synthesis results provides a better insight of the complexity of various features and what limits the performance of the HT tunnel
Keywords :
integrated circuit design; integrated circuit interconnections; open systems; chip-to-chip interconnect; hypertransport tunnel; packet reordering; Algorithm design and analysis; Ambient intelligence; Clocks; Cyclic redundancy check; Delay; Fabrics; Field programmable gate arrays; Frequency; Level control; Switches;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693515
