Architecture of a hypertransport tunnel

This paper presents a technology independent and open source hypertransport (HT) tunnel. HT is a high performance and low latency chip-to-chip interconnect standard. Various aspects of the architecture are presented, ranging from how functionality is spread over clock domains to the means of implementing a packet reordering algorithm. The analysis of synthesis results provides a better insight of the complexity of various features and what limits the performance of the HT tunnel