Title :
A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time
Author :
Wu, Chia-Tsun ; Wang, Wei ; Wey, I-Chyn ; Wu, An-Yeu
Author_Institution :
Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
Abstract :
This paper presents a frequency-estimation algorithm for the ADPLL designs instead of traditional binary frequency-search algorithm. With the proposed ADPLL architecture and synchronization process, the lock time can be optimized to two cycles. As the reference clock varies or frequency multiplication switches, lock time holds in two reference clock cycles. An implementation of proposed ADPLL design is realized in UMC 0.18 mum 1P6M CMOS technology with core area of 520times530 mum2. The PLL has the frequency range of 140 MHz to 1030 MHz with 22ps DCO resolution
Keywords :
CMOS integrated circuits; VLSI; digital phase locked loops; frequency estimation; oscillators; 0.18 micron; 140 to 1030 MHz; 520 micron; 530 micron; ADPLL designs; CMOS technology; frequency estimation algorithm; frequency multiplication switches; lock time; reference clock; synchronization process; traditional binary frequency-search algorithm; two-cycle lock-in time; Algorithm design and analysis; Clocks; Design engineering; Frequency conversion; Frequency estimation; Frequency synchronization; Frequency synthesizers; Phase locked loops; Switches; Time domain analysis;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693526
