Memory optimisations for high-resolution imaging

The rapid advance in imaging technology has led to the increasing availability of high-resolution digital images. For instance, the latest film scanners can produce more than 6 million pixels with 12-bit colour. We explore the opportunities of working with these high-resolution images on reconfigurable hardware, focusing on memory optimisations to support their effective processing. We consider template matching and related algorithms, and propose a runtime reconfiguration scheme which allows large template-matching algorithms to be implemented on small FPGAs. We present a partitioning scheme which allows the FPGA to process images larger than its local, external memory banks; alternatively, the scheme facilitates exploitation of concurrency offered by multiple memory banks in FPGA systems. We have developed parametric models to analyse these designs and to explore their potential. It is shown that, for instance, our column caching scheme can support linear speedup with respect to the number of columns, even when the reconfiguration time is large.