New pixel detectors for the upgrade of the ALICE Inner Tracking System

This contribution presents the on-going pixel detector R&D activities and results for the upgrade of the ALICE Inner Tracking System (ITS). Both hybrid and monolithic pixel detectors are being considered. The aim is to develop a detector with a pixel size in the order of 30×30 μm² (in the case of hybrid) or 20×20 μm² (in the case of monolithic), and an optimized readout architecture to achieve a low power consumption not exceeding -250 mW/cm². The material budget is another key issue of the new pixel detector: the design goal is to limit the overall material budget to 0.3% to 0.5% X₀ per layer. Two options are under study for the readout architectures: the rolling shutter and the sparsified readout. The rolling shutter envisages a periodical row by row readout of the pixel matrix, which is intrinsically dead-time free but with event pile-up if the readout rate is lower than the collision rate. The sparsified readout option is based on a segmentation of the pixel matrix into small sub-matrices with a readout time that scales with the event multiplicity. Several test structures and prototype front-end chips have been developed and produced by the TowerJazz foundry and are being tested in order to evaluate the performance and the radiation hardness of its 180 nm CMOS technology.