DocumentCode
2549213
Title
A 4-Kb low power 4-T SRAM design with negative word-line gate drive
Author
Wang, Chua-Chin ; Lee, Ching-Li ; Lin, Wun-Ji
Author_Institution
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung
fYear
2006
fDate
21-24 May 2006
Abstract
The physical implementation of a prototypical 250-MHz CMOS 4-T SRAM is described in this paper. The proposed SRAM cell takes advantage of a negative word-line gate drive to minimize the leakage current of the cell access transistors. As a result, the standby power consumption is drastically reduced. The proposed 4-Kb 4-T SRAM is measured to consume 0.12 mW in the standby mode, and a 3.8 ns access time in the R/W mode. The highest operating clock rate is measured to be 263 MHz
Keywords
CMOS memory circuits; SRAM chips; clocks; leakage currents; low-power electronics; 0.12 mW; 250 MHz; 263 MHz; 3.8 ns; CMOS 4-T SRAM; R/W mode; SRAM design; cell access transistors; leakage current; negative word-line gate drive; CMOS logic circuits; Capacitance; Circuit simulation; Energy consumption; Leakage current; Niobium; Power measurement; Random access memory; Threshold voltage; Time measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location
Island of Kos
Print_ISBN
0-7803-9389-9
Type
conf
DOI
10.1109/ISCAS.2006.1693537
Filename
1693537
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