Soft error hardening for logic-level designs

Vulnerability of combinational logic to soft errors exponentially increases with technology scaling. Reducing soft error susceptibility of logic gates comes with extra area, delay, and power consumption overhead that needs to be balanced in the entire circuit. In this paper, we present efficient soft error hardening techniques based on selective gate resizing to maximize soft error suppression for the entire logic-level design while minimizing area and delay penalties. Experimental results confirm that these techniques are able to highly reduce soft error rate with modest area and delay overhead