Title :
Network-on-chip link analysis under power and performance constraints
Author :
Kim, Manho ; Kim, Daewook ; Sobelman, Gerald E.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ.
Abstract :
This paper analyzes the behavior of interconnects in the highly structured environment of a network-on-chip (NoC). Two distinct classes of wires are considered, namely links between adjacent routers and links between a router and an attached processing element (PE). Analytical models for global router-to-router links and semi-global router-to-PE links are studied. Power and performance optimizations are obtained for each of these two classes of interconnections
Keywords :
integrated circuit interconnections; network routing; network-on-chip; interconnects; network-on-chip link analysis; performance constraint; power constraint; processing element; router; wires; Analytical models; Capacitance; Delay; Network-on-a-chip; Performance analysis; Physical layer; Pipeline processing; Repeaters; Throughput; Wire;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693546
