An improved frequency and phase synthesis architecture

A ring oscillator normally has multiple phase outputs which can be programmed into different frequencies with adjustable phase. This idea is implemented into "flying-adder" architecture (Mair and Xiu, 2000). However, this architecture has a timing violation issue and the phase synthesis range only covers half cycle of the output clock. This paper proposed an improved architecture in which these problems are solved and the phase synthesis range is expanded from half clock cycle into full clock cycle. Compared to the prior art (Mair and Xiu, 2000), the improved architecture is much more practical