Evaluating software and hardware implementations of signal-processing tasks in an FPGA

Finite impulse response (FIR) filtering and least mean squares (LMS) adaptive filtering algorithms have been implemented in both hardware and software on a Microblaze processor configured in a Virtex II, running uClinux. These implementations have been evaluated in terms of current usage (both idle and active), area usage (for hardware-assisted implementations), latency and CPU utilisation. Partitioning of the LMS algorithm was initially performed in a simple way, highlighting the shortcomings of obvious partitioning arrangements. A full implementation showed the advantages in terms of increased power efficiency (5.7mA consumed, compared to 60.4mA for the software implementation). Hardware implementations were found to be generally more power efficient, although increased idle power usage (11.3mA extra for the idle LMS implementation) may negate the savings if the task is not executed regularly.