DocumentCode
2549615
Title
Compact iterative FPGA Camellia algorithm implementations
Author
Denning, Daniel ; Irvine, James ; Devlin, Malachy
Author_Institution
Inst. of Syst. Level Integration, Livingston, UK
fYear
2004
fDate
6-8 Dec. 2004
Firstpage
311
Lastpage
314
Abstract
We present various iterative Camellia encryption algorithm implementations. The algorithm uses a 128-bit key, which keeps the algorithm as small as possible. The purpose for this implementation is for low-cost or area-restricted implementations suitable for embedded or mobile applications. We discuss the design and implementation considerations for a feedback architecture and achieve a throughput of 426Mbits/sec without key scheduling and 388Mbit/sec with key scheduling.
Keywords
cryptography; embedded systems; field programmable gate arrays; mobile computing; 128 bit; 128-bit key; 388 Mbit/s; 426 Mbits/s; embedded applications; feedback architecture; iterative Camellia encryption algorithm; iterative FPGA Camellia algorithm implementation; key scheduling; mobile applications; Cryptography; Digital signatures; Electronic government; Feedback; Field programmable gate arrays; Iterative algorithms; Portfolios; Public key; Scheduling; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on
Print_ISBN
0-7803-8651-5
Type
conf
DOI
10.1109/FPT.2004.1393287
Filename
1393287
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