Title :
Single bit error correction implementation in CRC-16 on FPGA
Author :
Shukla, Sunil ; Bergmann, Neil W.
Author_Institution :
Sch. of ITEE, Queensland Univ., Brisbane, Qld., Australia
Abstract :
Framing protocols employ cyclic redundancy check (CRC) to detect errors incurred during transmission. Generally whole frame is protected using CRC and upon detection of error, retransmission is requested. But certain protocols demand for single bit error correction capabilities for the header part of the frame, which often plays an important role in receiver synchronization. At a speed of 10 Gbps, header error correction implementation in hardware can be a bottleneck. This work presents a hardware efficient way of implementing CRC-16 over 16 bits of data, multiple bit error detection and single bit error correction on FPGA device.
Keywords :
cyclic redundancy check codes; data communication; error correction; error detection; field programmable gate arrays; synchronisation; 16 bits; CRC-16; FPGA device; cyclic redundancy check; framing protocols; header error correction; multiple bit error detection; receiver synchronization; single bit error correction; Australia; Cyclic redundancy check; Equations; Error correction; Field programmable gate arrays; Frequency; Hardware; Polynomials; Protection; Protocols;
Conference_Titel :
Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on
Print_ISBN :
0-7803-8651-5
DOI :
10.1109/FPT.2004.1393289